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| is61lsss51236, is61lsss102418 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 advance information rev. 00b 12/02/02 copyright ? 2002 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. advance information december 2002 quad 18mb 2x1b2 sdr seperate i/o sram features ? simultaneous read and write sigmaquad? in- terface dual single data rate interface echo clock outputs track data output drivers byte write controls sampled at data in time burst of 2 read and write single 1.8 v +150/?100 mv core power supply dedicated output supply voltage (v ddq ): 1.5 v or 1.8 v hstl interface pipelined read operation fully coherent read and write pipelines zq mode pin for programmable output drive strength jtag boundary scan (subset of ieee standard 1149.1) 165 pin (11x15), 1mm pitch, 13mm x 15mm ball grid array (bga) package pin compatible with future 36m, 72m and 144m devices sigmaram family overview these separate i/o sigmaquads are built in compli- ance with the sigmaram pinout standard for separate i/o synchronous srams. the first implementations are 18,874,368-bit (18mb) srams. these are the first in a family of wide, very low voltage hstl i/o srams designed to operate at the speeds needed to implement economical high performance networking systems. separate i/o sigmaquads are offered in a number of configurations. some emulate and enhance other synchronous separate i/o srams. this data sheet covers a higher performance sdr (single data rate) burst of 2 version. the logical defference between the protocols employed by these rams hinge mainly on various combinations of address bursting, output data registering, and write cueing. like the common i/o family of sigmarams, sigmaquad allow a user to implement the interface protocol best suited to the task at hand. speed -333 -300 -250 -200 tkhkh 3.0 3.3 4 5 ns tkhqv 1.6 1.8 2.1 2.3 ns bottom view 165-bump, 13 mm x 15mm bga 1 mm bump pitch, 11 x 15 bump array
is61lsss51236, is61lsss102418 issi ? 2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 12/02/02 clocking and addressing schemes a 2x1b2 sigmaquad is a synchronous device. it employs a single input register clock input k. the device also allows the user to manipulate the output register clock inputs quasi independently with the c clock inputs. if the c clock is tied high, the k clock is routed internally to fire the output registers instead. each 2x1b2 sigmaquad also supplies echo clock outputs, cq that is synchronized with read data output. when used in a source synchronous clocking scheme these echo clock outputs can be used to fire input registers at the data?s destination. because separate i/o 2x1b2 rams always transfer data in two packets, a0 is internally set to 0 for the first read or write transfer, and automatically incremented by 1 for the next transfer. since the lsb is tied off internally, the address field of a 2x1b2 ram is always one address pin less than the adver- tised index depth (e.g., the 1m x 18 has a 512k ad- dressable index). 1m x 18 sigmaquad sram top view 1234567891011 a dnu mcl/sa wbw1 mch nc r sa mcl/sa cq bnc q9 sa nc k bw0 sa nc nc q8 c nc nc d10 v ss sa sa v ss nc q7 d8 d nc d11 q10 v ss v ss v ss nc nc d7 e nc nc q11 v ddq v ss v ss v ss v ddq nc d6 q6 f nc q12 d12 v ddq v dd v dd v ddq nc nc q5 g nc d13 q13 v ddq v dd v dd v ddq nc nc d5 hnc v ref v ddq v ddq v dd v dd v ddq v ddq v ref zq j nc nc d14 v ddq v dd v dd v ddq nc q4 d4 k nc nc q14 v ddq v dd v dd v ddq nc d3 q3 l nc q15 v ddq v ss v ss v ddq nc q2 m nc nc d16 vss vss vss vss nc q1 d2 n nc d17 q16 v ss sa mch sa v ss nc d1 p nc nc q17 sa sa c sa sa nc d0 q0 r tdo tck sa sa sa sa sa sa sa tms tdi (144mb) nc/sa (36mb) (72mb) d9 v ss v ss v ss v ss v ss v ss v ss v ss d15 v ss nc 11 x 15 bump bga 13 x 15 mm2 body 1 mm bump pitch sa nc notes: 1. expansion addresses: a3 for 36mb, a10 for 72mb, a2 for 144mb 2. bw0 controls writes to d0:d8. bw1 controls writes to d9:d17. 3. dnu = do not use, mch = must connect high, mcl = must connect low. 4. it is recommended that h1 be tied low for compatibility with future devices. is61lsss51236, is61lsss102418 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 advance information rev. 00b 12/02/02 512 x 36 sigmaquad sram top view 1234567891011 a dnu mcl/sa w bw2 mch r mcl/sa cq b q27 q18 sa k bw0 sa d17 q17 q8 c d27 q28 d19 v ss sa sa sa v ss d16 q7 d8 d d28 d20 q19 v ss v ss v ss q16 d15 d7 e q29 d29 q20 v ddq v ss v ss v ss v ddq q15 d6 q6 f q30 q21 d21 v ddq v dd v dd v ddq d14 q14 q5 g d30 d22 q22 v ddq v dd v dd v ddq q13 d13 d5 h nc v ref v ddq v ddq v dd v dd v ddq v ddq v ref zq j d31 q31 d23 v ddq v dd v dd v ddq d12 q4 d4 k q32 d32 q23 v ddq v dd v dd v ddq q12 d3 q3 l q33 q24 v ddq v ss v ss d11 q11 q2 m d33 q34 d25 vss vss vss vss d10 q1 d2 n d34 d26 q25 v ss sa mch sa v ss d9 d1 p q35 d35 q26 sa sa c sa sa q9 d0 q0 r tdo tck sa sa sa sa sa sa sa tms tdi (288mb) nc/sa (72mb) (144mb) d18 v ss v ss v ss v ss v ss v ss v ss v ss d24 v ss q10 11 x 15 bump bga 13 x 15 mm2 body 1 mm bump pitch bw3 bw1 nc/sa (36mb) v ddq notes: 1. expansion addresses: a3 for 36mb, a10 for 72mb, a2 for 144mb 2. bw0 controls writes to d0:d8. bw1 controls writes to d9:d17. 3. bw2 controls writes to d18:d26. bw3 controls writes to d27:d35. 4. dnu = do not use, mch = must connect high, mcl = must connect low. 5. it is recommended that h1 be tied low for compatibility with future devices. is61lsss51236, is61lsss102418 issi ? 4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 12/02/02 pin description table symbol pin location description type comments sa b4, b8, c5, c6, c7, n5, n6, address input ? n7, p4, p5, p7, p8, r3, r4, r5, r7, r8, r9 sa a9 address input x18 version nc a9 no connect ? x36 version r a8 read input active low w a4 writes input active low bw0 - bw1 b7, a5 byte writes input active low x18 version nc a7, b5 no connect ? x18 version bw0 - bw3 b7, a7, a5, b5 byte writes input active low x36 version k b6 input clock input active high mch a6 much connect high input dc mode pin c p6 output clock input active high mch r6 much connect high input dc mode pin tms r10 test mode select input ? tdi r11 test data input input ? tck r2 test clock input input ? tdo r1 test data output output ? v ref h2, h10 hstk inputreference voltage input ? zq h11 output impedance matching input input ? mcl a2, a10 must connect low ? ? cq a11 echo clock output output echoes c or k clock dnu a1 do not use ? ? d0 - d35 b3, b9, c1, c3, c9, c11, d1 data inputs input x36 version d2, d10, d11, e2, e10, f3, f9, g1, g2, g10 g11, j1, j3, j9, j11, k2, k10, l3, l9, m1, m3, m9, m11, n1 n2, n10, n11, p2, p10 q0 - q35 b1, b2, b10, b11, c2, c10, data outputs output x36 version d3, d9, e1, e3, e9, e11, f1, f2 f10, f11, g3, g9, j2, j10, k1, k3, k9, k11, l1, l2, l10, l11, m2, m10, n3 n9, p1, p3, p9, p11 d0 - d17 b3, c3, c11, d2, d11, e10 data inputs input x18 version f3, g2, g11, j3, j11, k10, l3 m3, m11, n2, n11, p10 is61lsss51236, is61lsss102418 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 advance information rev. 00b 12/02/02 background separate i/o sigmarams have been designed to be closely related to common i/o sigmarams in pinout and overall architecture. the similarities give separate i/o sigmarams a cost advantage by allowing users and vendors to reuse supporting infrastructure and design elements. separate i/o sigmarams come in single and two double data rate configurations. because they are designed to operate with both the input data pins and the output data pins operating at full speed all the time, separate i/o sigmarams produce twice the bandwidth of common i/o srams of the same speed and output bus width. but because the bandwidth of a memory device is set by the architecture and performance of the core array, the bandwidth available from each port of a separate i/o sram is half the bandwidth available from the single port of an otherwise equivalent common i/o sram. separate i/o srams, from a system architecture point of view, are attractive in applications where alternating reads and writes are needed. therefore, the sigmaram separate i/o interface and truth table are optimized for alternating reads and writes. separate i/ o srams are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from separate i/o srams cut the ram?s bandwidth in half. a separate i/o sigmaram can begin an alternating sequence of reads and writes with either a read or a write. in order for any separate i/o sram that shares a common address between it?s two ports to keep both ports running all the time, the ram must implement some sort of burst transfer protocol. the burst must be at least long enough to cover the time the opposite port is receiving instructions on what to do next. the rate at which a ram can accept a new random address is the most fundamental performance metric for the ram. each of the three separate i/o sigmarams support the same address rate because random address rate is determined by the internal performance of the ram and they are all based on the same internal circuits. differences between the truth tables of the different separate i/o sigmarams, or any other separate i/o srams, follow from differences in how the ram?s interface is contrived to interact with the rest of the system. each mode of operation has it?s own advan- tages and disadvantages. the user should consider the nature of the work to be done by the ram to evaluate which version is best suited to the application at hand. pin description table symbol pin location description type comments q0 - q17 b2, b11, c10, d3, e3, e11, f2 data output output x18 version f11, g3, j10, k3, k11, l2, l11 m10, n3, p3, p11 nc b1, b9, b10, c1, c2, c9, d1 no connect ? x18 version d9, d10, e1, e2, e9, f1, f9 f10, g1, g9, g10, j1, j2 j9, k1, k2, k9, l1, l9, l10, m1 m2, m9, n1, n9, n10, p1, p2, p9 nc a3, h1 no connect ? ? v dd f5, f7, g5, g7, h5, h7, j5, j7, power supply supply 1.8 v nominal k5, k7 v ddq e4, e8, f4, f8, g4, g8, output buffer supply supply 1.5 v nominal h3, h4, h8, h9, j4, j8, k4, k8, l4, l8 v ss c4, c8, d4, d5, d6, d7, d8, e5 ground supply ? e6, e7, f6, g6, h6, j6, k6, l5, l6 l7, m4, m5, m6, m7, m8, n4, n8 note: nc = not connected to die or any other pin is61lsss51236, is61lsss102418 issi ? 6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 12/02/02 although the separate i/o sigmaram family of pinouts has been designed to support single and double data rate options, not allsigmaram implementations will support both protocols. the following timing diagrams provide a quick comparison between the sdr and ddr protocol options available in the context of the separate sigmaram standard. this particular data sheet covers the single data rate burst of 2 ( 2x1b2) separate i/o sigmaram. the character of the applications for fast synchronous srams in networking systems are extremely diverse. sigmarams ha been developed to address the diverse needs of the networking market in a manner that can be supported with a unifie development and manufac- turing infrastructure. sigmarams address each of the bus protocol options commonly found in networking systems. alternating read-write operations separate i/o sigmarams follow a few simple rules of operation. - read or write commands issued on one port are never allowed to interrupt a operation in progress on the other port. - read or write data transfers in progress may not be interrupted and re-started. - a read of a given address location immediately after the location has just been written produces the just- written data. (i.e. sigmarams are ?coherent?.) - r and w high always deselects the ram but does not disable the cq or cq output pins. - all address, data, and control inputs are sampled on clock edges. in order to enforce these rules, each ram combines present state information with command inputs. see the truth table for details. is61lsss51236, is61lsss102418 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 advance information rev. 00b 12/02/02 2x1b2 - single data rate separate i/o sigmaram read first 2x1b2 sigmaquad sram sdr read the status of the address input, w , and r pins are sampled at each rising edge of k. w and r high causes chip disable. a low on the read enable-bar pin, r , begins a read cycle. r is always ignorned if the previous command loaded was a read command. xx b c d e f no o p read write read write read k address r w bwx d c q cq dc0 dc1 de0 qb0 qb1 qd0 the two resulting data output transfers begin after the next rising edge of the k clock. data is clocked out by the next rising edge of the c and by the rising edge of the c that follows. is61lsss51236, is61lsss102418 issi ? 8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 12/02/02 2x1b2 sigmaquad sram sdr write the status of the adress input, w , and r pins are sampled at each rising of k. w and r high causes chip disable. a low on the write enable-bar pin, w , and a high on the read enable-bar pin, r , begins a write 2x1b2 double data rate separate i/o sigmaram write first xx b c d e f k address r w bwx d c q cq no op write read write read write db0 db1 dd0 dd1 qc0 qc1 cycle. w is always ignored if the previous command was a write command. data is clocked in by the next rising edge of k and by the rising edge of the k that follows. is61lsss51236, is61lsss102418 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 advance information rev. 00b 12/02/02 special functions byte write control byte write enable pins are sampled at the same time that data in is sampled. a high on the byte write enable pin associated with a particular byte (e.g. bw0 controls d0- d8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. any or all of the byte write enable pins may be driven high or low during the data in sample times in a write sequence. each write enable command and write address loaded into the ram provides the base address for a 4 beat data transfer. the x18 version of the ram, for example, may write 72 bits in association with each address loaded. any 9 bit byte may be masked in any write sequence. ram write sequence using byte write enables (x18) data in sample time bw0 bw0 bw0 bw0 bw0 bw1 bw1 bw1 bw1 bw1 d0-d8 d9-d17 beat 1 0 1 data in don't care beat 2 1 0 don't care data in resulting write operation byte1 byte 2 byte 3 byte 4 d0-d8 d9-d17 d0-d8 d9-d17 written u nchanged unchanged w ritten output register control separate i/o sigmarams offer two mechanisms for controlling the output data registers. typically control is handled by the output register clock input c. the output register clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the k clock. if the c clock input is tied high, the ram reverts to k control of the outputs, allowing the ram to function as a conventional pipelined read sram. echo clock sigmarams feature echo clocks, cq and cq, that track the performance of the output drivers. the echo clocks are delayed copies of the output register clock, c. echo clocks are designed to track changes in output driver delays due to variance in die tempera- ture and supply voltage. the echo clocks are designed to fire with the rest of the data output drivers. sigmarams provide both in-phase, or true, echo clock outputs (cq) and inverted echo clock outputs ( cq ). echo clocks are always active neither inhibiting reads via holding r high, nor deselection of the ram via holding r and w high will deactivate the echo clocks. is61lsss51236, is61lsss102418 issi ? 10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 12/02/02 four bank depth expansion schematic a r k w d q c cq bank 0 bank 1 bank 2 bank 3 a 0 -an k d1-dn c a r k w d q c cq a r k w d q c cq a r k w d q c cq q 1 - qn cq 0 cq 1 cq 2 cq 3 r 3 w 0 r 0 w 1 w 3 r 2 w 2 r 1 note: for simplicity bwn is not shown is61lsss51236, is61lsss102418 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 advance information rev. 00b 12/02/02 sigmaram depth expansion no op read write read write read write bank 2 bank2 bank1 bank 2 bank1 bank 1 xx b c d e f g dc0 dc1 de0 de1 r 1 q bank 1 q bank 2 q bank 1+ q bank 2 cq bank 1 cq bank 2 d bank 1 d bank 2 r 2 w 1 w 2 address k c qd0 qd1 qb0 qb1 qb0 qb1 qd0 qd1 is61lsss51236, is61lsss102418 issi ? 12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 12/02/02 separate i/o 2x1b2 sigmaquad sram truth table a r r r r r w w w w w previous operation current operation d d q q k k k k k k k k k (t n )(t n )(t n )(t n-1 )(t n )(t n+1 )(t n+2 )(t n+1 )(t n+2 ) x 1 1 deselect deselect x ? hi-z ? x 1 x write deselect d1 ? hi-z ? x x 1 read deselect x ?q2? v 1 0 deselect write d0 d1 hi-z ? v 0 x deselect read x ?q0q1 v x 0 read w rite d0 d1 q1 ? v 0 x write read d1 ?q0q1 note: 1. "1" = input "high"; "0" = input "low"; "v" = input "vaild"; "x" = input "don't care" 2. " ?" indicates that the input requirement or output state is determined by the next operation. 3. q0 and q1 indicate the first, second, third, and fourth pieces of output data transferred during read operations. 4. d0 and d1 indicate the first, second, third, and fourth pieces of input data transferred during write operations. 5. qs are tri-stated for one cycle in respones to deselect and write commands, one cycle after the command is sampled, except when preceded by a read command. 6. cqs are never tri-stated. 7. users should not clock in metastable addresses. x18 btye write clock truth table bw bw bw bw bw bw bw bw bw bw current operation d d k k k k k (t n+1 )(t n+2 )(t n )(t n+1 )(t n+2 ) t t write d1 d2 dx stored if bwn = 0 in all four data transfers t f write d1 x dx stored uf bwn = 0 in 1st data transfer only f f write x x dx stored if bwn = 0 in 2nd data transfer only f f write abort x x no dx stored in any of the four data transfers note: 1. "1" = input "high"; "0" = input "low"; "x" = input "don't care"; "t" = input "true"; "f" = input "false". 2. if one or more bw n = 0 then bw = "t" else bw = "f" is61lsss51236, is61lsss102418 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 13 advance information rev. 00b 12/02/02 output driver impedance control hstl i/o sigmarams are supplied with programmable impedance output drivers. the zq pin must be con- nected to vss via an external resistor, rq, to allow the sram to monitor and adjust its output driver imped- ance. the value of rq must be 5x the value of the intended line impedance driven by the sram. the allowable range of rq to guarantee impedance match- ing with a vendor specified tolerance is between 150 ? and 300 ? . periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. a clock cycle counter periodically triggers an impedance evaluation, resets and counts again. each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. the output driver is implemented with discrete binary weighted impedance steps. impedance updates for ?0s? occur whenever the sram is driving ?1s? for the same do?s (and vice-versa for ?1s?) or the sram is in hi-z. the sram requires 32k start-up cycles, selected or deselected, after v dd reaches its operating range to reach its programmed output driver impedance. x18 byte write enable ( bwn bwn bwn bwn bwn ) truth table bw0 bw0 bw0 bw0 bw0 bw1 bw1 bw1 bw1 bw1 d0-d8 d9-d17 1 1 don't care don't care 0 1 data in don't care 1 0 don't care data in 0 0 data in data in x36 byte write enable truth table b b b b b w0 w0 w0 w0 w0 bw1 bw1 bw1 bw1 bw1 bw2 bw2 bw2 bw2 bw2 bw3 bw3 bw3 bw3 bw3 d0-d8 d9-d17 d18-d26 d27-d35 1 1 1 1 don't care don't care don't care don't care 0 1 1 1 data in don't care don't care don't care 1 0 1 1 don't care data in don't care don't care 0 0 1 1 data in data in don't care don't care 1 1 0 1 don't care don't care data in don't care 0 1 0 1 data in don't care data in don't care 1 0 0 1 don't care data in data in don't care 0 0 0 1 data in data in data in don't care 1 1 1 0 don't care don't care don't care data in 0 1 1 0 data in don't care don't care data in 1 0 1 0 don't care data in don't care data in 0 0 1 0 date in data in don't care data in 1 1 0 0 don't care don't care data in data in 1 1 0 0 dont' care don't care data in data in 0 1 0 0 data in don't care data in data in 1 0 0 0 don't care data in data in data in 0 0 0 0 data in data in data in data in is61lsss51236, is61lsss102418 issi ? 14 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 12/02/02 absolute maximum ratings (all voltages reference to gnd ) symbol description value unit v dd voltage on v dd pins ?0.5 to 2.5 v v ddq voltage in v ddq pins ?0.5 to 2.3 v v i/o voltage on i/o pins ?0.5 to v ddq +0.5 ( 2.3 v max.) v v in voltage on other input pins ?0.5 to v ddq +0.5 ( 2.3 v max.) v i in input current on any pin 100 ma dc i out output current on any pin 100 ma dc t j maximum junction temperature 125 c t stg storage temperature -55 to 125 c note: permanent device damage may occur if absolute maximum ratings are exceeded. operation should be limited to recommended operating conditions. exposure to conditions exceeding recommended operating conditions, for an extended period of time, may affect reliability of this component. power supply characteristics (t a = 0 min., 25 typ, 70 max c) symbol parameter min. typ. max. unit v dd supply voltage 1.7 1.8 1.9 v v ddq (1) 1.8 v i/o supply voltage 1.7 1.8 v dd v 1.5 v i/o supply voltage 1.4 1.5 1.6 v v note: 1. unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 v v ddq 1.6v (i.e., 1.5 v i/o) and 1.7 v v ddq 1.9 v (i.e., 1.8 v i/o) and quoted at whichever condition is worst case. 2. the power supplies need to be powered up in the following sequence: v dd , v ddq , v ref , followed by signal inputs. the power down sequence must be the reverse. v ddq must not exceed v dd . is61lsss51236, is61lsss102418 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 15 advance information rev. 00b 12/02/02 hstl i/o dc input characteristics symbol parameter min. typ. max. unit v ih input high voltage v ref + 200 ? ?mv v il input low voltage ? ? v ref + 200 mv v dif clock input differential voltage 400 ? ? mv v ref v ref dc v oltage v dd (min)/2 ?v ddq (max)/2 mv note: 1. the peak to peak ac component superimposed on v ref may not exceed 5% of the dc component of v ref . 2. sram performance is a function of clock input differential voltage ( v dif ). 3. to guarantee ac characteristics, v ih , v il , trise and tfall of inputs and clocks must be within 10% of each other. 4. for devices supplied with hstl i/o input buffers. compatible with both 1.8v and 1.5v i/o drivers. 5. see ac input definition drawing below. i/o capacitance (t a = 25 c, f = 1 mh z ) symbol parameter test conditions min. max. unit c a address input capacitance v in = 0 v ? 3.5 pf c b control input capacitance v in = 0 v ? 3.5 pf c ck clock input capacitance v in = 0 v ? 3.5 pf c dq data output capacitance v out = 0 v ? 4.5 pf c cq cq clock output capacitance v out = 0 v ? 4.5 pf note: these parameters are sampled and not 100% tested. is61lsss51236, is61lsss102418 issi ? 16 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 12/02/02 ac test conditions (v dd = 1.8v 0.1v, t a = 0 to 85c) parameter symbol conditions units v ddq 1.5v0.1 1.8 0.1 v v ref peak to peak ac votlage (1) 5% v ref (dc) 5% v ref (dc) mv input high level (2,3) v ih 1.25 1.4 v input low level (2,3) v ih 0.25 0.4 v input rise & fall time 2.0 2.0 v/ns clock input differential voltage (2,3) 800 800 mv input reference level 0.75 0.9 v clock input high voltage v kih 1.25 1.4 v clock input low voltage v kil 0.25 0.4 v clock input rise & fall time 2.0 2.0 v/ns clock input reference level 0.75 0.9 v output reference level 0.75 0.9 v output load conditions zq = v ih see below see below notes: 1. the peak to peak ac component superimposed on v ref may not exceed 5% of the dc component of v ref . 2. sram performance is a function of clock input differential voltage ( v ref ). the ram can be operated with a single ended clocking with either k or k tied to v ref . 3. to guarantee ac characteristics, v ih , v ih ,trise and tfall of inputs and clocks must be within 10% of each other. 4. for devices supplied with hstl i/o input buffers. compatible with both 1.8v and 1.5v i/o drivers. 5. see ac input definition drawing below. v ih (ac) v ref v il (ac) v dif hstl i/o ac input definitions is61lsss51236, is61lsss102418 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 17 advance information rev. 00b 12/02/02 ac test loads undershoot measurement and timing overshoot measurement and timing 20% t kc 50% gnd v ih gnd - 1.0v 20% t kc 50% v cc + 1.0v v cc v il ac test conditions parameter unit input pulse level v ddq input low level 0v max. input slew rate 2v/ns input and output timing v ddq /2 and reference level dq vt = v ddq /2 50 ? rq = 250 ? (hstl i/o) is61lsss51236, is61lsss102418 issi ? 18 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 12/02/02 selectable impedance output driver dc electrical characteristics symbol parameter min. max. units v oh output high voltage (1,3) v ddq /2 v ddq v v ol output low voltage (2,3) v ss v ddq /2 v notes: 1. i oh = (v ddq /2) / (rq / 5) +/- 15% @ v oh = v ddq /2 (for: 150 ? rq 300 ? ). 2. i ol = ( v ddq /2 ) / (rq / 5) +/- 15% @ v ol = v ddq /2 (for: 150 ? rq 300 ? ). 3. parameter tested with rq=250 ? and v ddq = 1.5 v or 1.8v input and output leakage characteristics symbol parameter test conditions min. max. units i il input leakage current v in = 0 to v dd ?2 2 a (except mode pins) i inm mode pin input current v dd v in v il ?100 2 a 0v v in v il ?2 2 i ol output leakage current output disable, ?2 2 a v out = 0 to v ddq operating currents (t a = 0 to 70 c commerical, t a = -40 to 85 c industrial) symbol par ameter test conditions -333 -300 -250 -200 units com. ind. com. ind. com. ind. com ind. i dd operating current ce1 < v il max. tbd ma t khkh > t khkh min. all other inputs v il = v in > v ih i sb 1 bank deselect current ce1 < v ih min. or tbd ma & & ce2 or ce3 false tbd i sb 2 chip disable current t khkh > t khkh min. all other inputs v il > v in > v ih i dd 3 cmos deselect current device deselected tbd ma all inputs tbd vss+0.10v > v in > v dd ?0.10v i dd average power supply i out = 0ma tbd ma operating current v in = v ih or v il tbd i dd 2 power supply deselect i out = 0ma tbd ma operating current v in = v ih or v il power measured with output pins floating. is61lsss51236, is61lsss102418 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 19 advance information rev. 00b 12/02/02 ac electrical characteristics -333 -300 -250 symbol parameter min max min max min max unit t khkh input clock cycle time 3.0 ? 3.3 ? 4.0 ? ns t chch output clock cycle time 3.0 ? 3.3 ? 4.0 ? ns t khkl input clock high time 1.2 ? 1.3 ? 1.6 ? ns t clcl output clock high time 1.2 ? 1.3 ? 1.6 ? ns t khkh input clock low time 1.2 ? 1.3 ? 1.6 ? ns t clch output clock low time 1.2 ? 1.3 ? 1.6 ? ns t khch input clock high to output clock high 0 2.0 0 2.2 0 2.6 ns t klcl input clock low to output clock low 0 2.0 0 2.2 0 2.6 ns t chqv output clock high to output valid ? 1.6 ? 1.8 ? 2.1 ns t clqv output clock low to output valid ? 1.6 ? 1.8 ? 2.1 ns t chqz output clock high to output in high-z 0.5 1.6 0.5 1.8 0.5 2.1 ns t clqx output clock low to output invalid 0.5 ? 0.5 ? 0.5 ? ns t chqx output clock high to output invalid 0.5 ? 0.5 ? 0.5 ? ns t chqx 1 output clock high to output in low-z 0.5 ? 0.5 ? 0.5 ? ns t chcqx 1 output clock high to echo clock low-z 0.5 ? 0.5 ? 0.5 ? ns t chcqh output clock high to echo clock high 0.5 1.5 0.5 1.7 0.5 2.0 ns t clcql output clock low to echo clock low 0.5 1.5 0.5 1.7 0.5 2.0 ns t cqhqx echo clock high to output invalid -0.2 ? -0.2 ? -0.25 ? ns t cqlqx echo clock low to output invalid -0.2 ? -0.2 ? -0.25 ? ns t cqhqv echo clock high to output valid ? 0.2 ? 0.2 ? 0.25 ns t cqlqx echo clock low to output invalid -0.2 ? -0.2 ? -0.25 ? ns t cqlqv echo clock low to output valid ? 0.2 ? 0.2 ? 0.25 ns t khcqz input clock high to echo clock high-z 0.5 1.5 0.5 1.7 0.5 2.0 ns t chcqz output clock high to echo clock high-z 0.5 1.5 0.5 1.7 0.5 2.0 ns t cqhcql echo clock high time t chcl 100 ps t chcl 100 ps t chcl 100 ps ns t cqlcqh echo clock low time t clch 100 ps t clch 100 ps t clch 100 ps ns t cqhcql 2 echo clock high time t khkl 100 ps t khkl 100 ps t khkl 100 ps ns t cqlcqh 2 echo clock low time t klkh 100 ps t klkh 100 ps t klkh 100 ps ns t khqv input clock high to ouput valid ? 1.6 ? 1.8 ? 2.1 ns t klqv input clock low to ouput valid ? 1.6 ? 1.8 ? 2.1 ns t khqz input clock high to output in high-z 0.5 1.6 0.5 1.8 0.5 2.1 ns t khqx input clock high to output invalid 0.5 ? 0.5 ? 0.5 ? ns t klqx input clock low to output invalid 0.5 ? 0.5 ? 0.5 ? ns t khqx 1 input clock high to output in low-z 0.5 ? 0.5 ? 0.5 ? ns t khcqx 1 input clock high to echo clock low-z 0.5 ? 0.5 ? 0.5 ? ns is61lsss51236, is61lsss102418 issi ? 20 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 12/02/02 -333 -300 -250 symbol parameter min max min max min max unit t khcqh input clock high to echo clock high 0.5 1.5 0.5 1.7 0.5 2.0 ns t khcql input clock low to echo clock low 0.5 1.5 0.5 1.7 0.5 2.0 ns t avkh address vailid to input clock high 0.6 ? 0.7 ? 0.8 ? ns t ahax input clock high to address don't care 0.4 ? 0.4 ? 0.5 ? ns t ivkh r , w or e input valid to input clock high 0.6 ? 0.7 ? 0.8 ? ns t khix input clock high to r , w or e don't care 0.4 ? 0.4 ? 0.5 ? ns t dvkh data in and b x valid to input clock high 0.32 ? 0.35 ? 0.45 ? ns t khdx input clk high to datain & b x don't care 0.27 ? 0.30 ? 0.35 ? ns t dvkl data in and b x valid to input clock low 0.32 ? 0.35 ? 0.40 ? ns t kldx input clk low to datain & b x don't care 0.27 ? 0.30 ? 0.35 ? ns notes: 1. measured at 100 mv from steady state. not 100% tested. 2. guaranteed by design. not 100% tested. 3. for any specific temperature and voltage t chcqz < t chqcx 1 and t khcqz < t khcqx 1. 4. tested using ac test load b. is61lsss51236, is61lsss102418 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 21 advance information rev. 00b 12/02/02 read cycle timing using c to control output data qa0 k a c q cq a b c = cq high z tkhch tchcl tclch tchch tchqv tchqz tchqx1 tchqx tchcqh tclcql tcqhqx tcqhqv tchcqz tcqhcql tcqlcqh tchcqx1 tklcl is61lsss51236, is61lsss102418 issi ? 22 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 12/02/02 read cycle timing using k to control output data k a q cq a b c = cq high z qa0 tkhax tkhkl tklkh tkhkh tkhqv tkhqz tkhqx1 tkhqx tkhcqh tklcql tcqhqx tcqhqv tkhcqz tcqhcql2 tcqlcqh2 tkhcqx1 tavkh note: when k is used to control output data, c should be tied "high" (not shown). is61lsss51236, is61lsss102418 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 23 advance information rev. 00b 12/02/02 control and data in timing a b c tkhax tavkh tkhix tivkh da0 da1 tkhdx tdvkh k a r, w d, b x is61lsss51236, is61lsss102418 issi ? 24 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 12/02/02 jtag port operation overview the jtag port on this ram operates in a manner consistent with ieee standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as jtag), but does not implement all of the func- tions required for 1149.1 compliance. unlike jtag implementations that have been common among sram vendors for the last several years, this implementation does offer a form of extest, known as clock assisted extest, reducing or eliminating the ?hand coding? that has been required to overcome the test program compiler errors caused by previous non-compliant implementations. jtag pin descriptions pin pin name i/o description tck test clock in clocks all tap events. all inputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms test mode select in the tms input is sampled on the rising edge of tck. this is the command input for the tap controller. an undriven tms input will produce the same result as a logic one input level. tdi test data in in the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is determined by the state of the tap controller and the instruction that is currently loaded in the tap instruction register (refer to the tap controller state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out out output that is active depending on the state of the tap controller. output changes in response to the falling edge of tck. this is the output side of the serial registers placed between tdi and tdo. note: this device does not have a trst (tap reset) pin. trst is optional in ieee 1149.1. the test-logic-reset state is entered while tms is held high for five rising edges of tck. the tap controller is also reset automaticly at power-up. disabling the jtag port it is possible to use this device without utilizing the jtag port. the port is reset at power-up and will remain inactive unless clocked. to assure normal operation of the ram with the jtag port unused, tck should be tied low, tdi and tms may be left floating or tied to v dd . tdo should be left unconnected. is61lsss51236, is61lsss102418 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 25 advance information rev. 00b 12/02/02 jtag tap block diagram bypass register instruction register id code register boundary scan register . . . . . . . . 0 2 1 0 31 30 29 2 1 0 n 2 1 0 test access port (tap) controller tdi tms tck tdo jtag port registers overview the jtag registers, refered to as test access port (tap) registers, are selected (one at a time) via the sequences of 1s and 0s applied to tms as tck is strobed. each of the tap registers are serial shift registers that capture serial input data on the rising edge of tck and push serial data out on the next falling edge of tck. when a register is selected, it is placed between the tdi and tdo pins. instruction register the instruction register holds the instructions that are executed by the tap controller when it is moved into the run, test/idle, or the various data register states. in- structions are 3 bits long. the instruction register can be loaded when it is placed between the tdi and tdo pins. the instruction register is automatically preloaded with the idcode instruction at power-up or whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single-bit register that can be placed between tdi and tdo. it allows serial test data to be passed through the ram?s jtag port to another device in the scan chain with as little delay as possible. boundary scan register the boundary scan register is a collection of flip flops that can be preset by the logic level found on the ram?s input or i/o pins. the flip flops are then daisy chained together so the levels found can be shifted serially out of the jtag port?s tdo pin. the boundary scan register also includes a number of place holder flip flops (always set to a logic 1). the relationship between the device pins and the bits in the boundary scan register is described in the following scan order table. the boundary scan register, under the control of the tap controller, is loaded with the contents of the rams i/o ring when the controller is in capture-dr state and then is placed between the tdi and tdo pins when the controller is moved to shift-dr state. sample-z, sample/preload and extest instructions can be used to activate the boundary scan register. is61lsss51236, is61lsss102418 issi ? 26 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 12/02/02 identification (id) register the id register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction register. the code is loaded from a 32-bit on-chip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when the controller is moved into shift-dr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. bit # 31302928 2726 2524 2322 212019 1817 161514 1312 1110 9 8 7 6 5 4 3 2 1 0 x18 0 00000000000000001 1000011010101 1 x36 0 00000000000000010 1000011010101 1 presence register die i/o issi technology revision not used configuration jedec vendor code id code id register contents boundary scan exit order table order pin id o rder pin id o rder pin id o rder pin id o rder pin id 1 6r 23 10k 45 9b 67 3b 89 2k 2 6p 24 9j 46 10b 68 1c 90 1k 3 6n 25 9k 47 11a 69 1b 91 2l 4 7p 26 10j 48 10a 70 3d 92 3l 5 7n 27 11j 49 9a 71 3c 93 1m 6 7r 28 11h 50 8b 72 1d 94 1l 7 8r 29 10g 51 7c 73 2c 95 3n 88p 309g 526c 743e 96 3m 9 9r 31 11f 53 8a 75 2d 97 1n 10 11p 32 11g 54 7a 76 2e 98 2m 11 10p 33 9f 55 7b 77 1e 99 3p 12 10n 34 10f 56 6b 78 2f 100 2n 13 9p 35 11e 57 6a 79 3f 101 2p 14 10m 36 10e 58 5b 80 1g 102 1p 15 11n 37 10d 59 5a 81 1f 103 3r 16 9m 38 9e 60 4a 82 3g 104 4r 17 9n 39 10c 61 5c 83 2g 105 4p 18 11l 40 11d 62 4b 84 1h 106 5p 19 11m 41 9c 63 3a 85 1j 107 5n 20 9l 42 9d 64 2a 86 2j 108 5r 21 10l 43 11b 65 1a 87 3k 109 22 11k 44 11c 66 2b 88 3j 1 active extoe is61lsss51236, is61lsss102418 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 27 advance information rev. 00b 12/02/02 tap controller instruction set overview tthere are two classes of instructions defined in the standard 1149.1-1990; standard (public) instructions, and device specific (private) instructions. some public instructions are mandatory for 1149.1 compliance. op- tional public instructions must be implemented in pre- scribed ways. although the tap controller in this device follows the 1149.1 conventions, it is not 1194.1-compliant because one of the mandatory instructions, extest, is uniquely implemented. the tap on this device may be used to monitor all input and i/o pads. this device will not perform intest but can perform the preload portion of the sample/preload command. when the tap controller is placed in capture-ir state, the two least significant bits of the instruction register are loaded with 01. when the controller is moved to the shift-ir state, the instruction register is placed between tdi and tdo. in this state the desired instruc- tion is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions, the tap executes newly loaded instruc- tions only when the controller is moved to update-ir state. the tap instruction set for this device is listed in the following table. jtag tap controller state diagram select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 11 1 11 11 1 1 1 1 1 1 1 0 0 0 0 1 00 0 0 0 0 0 0 0 0 0 10 is61lsss51236, is61lsss102418 issi ? 28 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 12/02/02 instruction descriptions bypass when the bypass instruction is loaded in the instruc- tion register, the bypass register is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. sample/preload sample/preload is a standard 1149.1 mandatory public instruction. when the sample / preload instruction is loaded in the instruction register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the bound- ary scan register. some boundary scan register locations are not associated with an input or i/o pin, and are loaded with the default state identified in the bsdl file. because the ram clock is independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e. in a metastable state). although allowing the tap to sample metastable inputs will not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the tap?s input data capture set- up plus hold time (tts plus tth ). the ram?s clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the bound- ary scan register. moving the controller to shift-dr state then places the boundary scan register between the tdi and tdo pins. the update-dr controller state transfers the contents of boundary scan cells into the holding register of each cell associated with an output pin on the ram. extest extest is an ieee 1149.1 mandatory public instruc- tion. it is to be executed whenever the instruction register is loaded with all logic 0s. the extest command does not block or override the ram?s input pins; therefore, the ram?s internal state is still deter- mined by its input pins. typically, the boundary scan register is loaded with the desired pattern of data with the sample/preload command. then the extest command is used to output the boundary scan register?s contents, in parallel, on the ram?s data output drivers on the falling edge of tck when the controller is in the update-ir state. alternately, the boundary scan register may be loaded in parallel using the extest command. when the extest instruction is selected, the state of all the ram?s input and i/o pins, as well as the default values at scan register locations not associated with a pin, are sampled and transferred in parallel into the bound- ary scan register on the rising edge of tck in the capture-dr state. boundary scan register con-tents may then be shifted serially through the register using the shift-dr command or the controller can be skipped to the update-dr com-mand. when the controller is placed in the update-dr state, a ram that has a fully compliant extest function drives out the value of the boundary scan register location associated with which each output pin. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi and tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test- logic-reset state. sample-z/preload the sample-z instruction operates exactly like sample/preload except that loading the sample-z instruction forces all the ram?s output drivers, except tdo, to an inactive drive state (high-z). rfu these instructions are reserved for future use. in this device they replicate the bypass instruction. is61lsss51236, is61lsss102418 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 29 advance information rev. 00b 12/02/02 jtag dc recommended operating conditions (t a = 0 to 85c) symbol parameter test conditions min. max. unit v tih jtag input high voltage (1) 0.65*v dd v dd +0.3 v v til jtag input low voltage (1) -0.3 0.35*v dd v v toh jtag output high voltage (2) cmos i toh = -100 ? v dd -0.1 ? v ttl i toh = -8m v dd -0.4 ? v tol jtag output low voltage cmos i tol = 100 ? ? 0.1 v ttl i tol = 8m ? 0.4 i olt jtag output leakage current output disable 2 2 ? v out = 0v to v dd i inth jtag input leakage current v dd >v in >v il -100 2 ? i intl jtag input leakage current 0v is61lsss51236, is61lsss102418 issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 31 advance information rev. 00b 12/02/02 jtag port ac electrical characteristics symbol parameter min max unit t tkc tck cycle time 50 ? ns t tkq tck low to tdo valid ?20 ns t tkh tck high pulse width 20 ? ns t tkl tck low pulse width 20 ? ns t ts tdi & tms set up time 10 ? ns t th tdi & tms hold time 10 ? ns jtag port timing diagram tck tms tdi tdo t tkh t tkl t tkc t ts t th t tkq is61lsss51236, is61lsss102418 issi ? 32 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 12/02/02 issi ? integrated silicon solution, inc. 2231 lawson lane santa clara, ca 95054 tel: 1-800-379-4774 fax: (408) 588-0806 e-mail: sales@issi.com www.issi.com ordering information commercial range: 0 c to +70 c frequency order part no. package x18 250 IS61LSSS102418-250B 209-pin bga 300 is61lsss102418-300b 209-pin bga 333 is61lsss102418-333b 209-pin bga x36 250 is61lsss51236-250b 209-pin bga 300 is61lsss51236-300b 209-pin bga 333 is61lsss51236-333b 209-pin bga industrial range: -40 c to +85 c frequency speed (ns) order part no. package tbd |
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